Oscaria Audio / Taktwerk RTOS
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Taktwerk RTOS

Rhythm engine for real-time audio processing on STM32. Lightweight, preemptive, deterministic — built for low-latency audio/control systems where timing is the product.

Preemptive Deterministic Audio-focused

Specs

Compact on purpose. Static-friendly. Designed around predictable scheduling and fast ISR-to-task signaling.

License: MIT
Platform: STM32 (focus: STM32F4)
CPU: ARM Cortex-M4
Scheduling: Preemptive, priority-based
Priorities: 32 levels (0 = highest)
Round-robin: Within same priority (time quanta)
Task selection: O(1) via bitmap + CLZ
Memory model: User-allocated (no malloc by design)

What it’s for

Audio synthesizers, effects processors, drum machines — and any embedded application that needs precise, low-jitter real-time behavior with minimal runtime overhead.


Key features

Real-time scheduling

Preemptive priority scheduling with round-robin per priority. Deterministic selection using a priority bitmap and the Cortex-M CLZ instruction.

Scheduler
Model: 32 priority levels
Policy: Round-robin within same level
Goal: Predictable context switching
Use case: Audio/control split (ISR → audio task)
Implementation: Bitmap + CLZ fast path
Timing: Low overhead, jitter-aware

Synchronization primitives

Mutex locks with priority inheritance to prevent unbounded priority inversion — critical for real-time audio.

Mutex
Mutex: Priority inheritance protocol
Effect: Priority boosting on contention
Goal: Keep latency bounded
Target: ISR-safe coordination patterns
Design: Small + predictable
Notes: Avoid heavy locking in audio paths

Software timers

Callback-based timers for periodic or one-shot events. User-allocated (no malloc) for deterministic memory. Callbacks run in ISR context — keep them short.

Timers
Modes: One-shot + periodic
Ops: O(1) start/stop
Patterns: Watchdog-style reset
Use cases: Debounce, timeouts, periodic checks
Context: ISR callback
Guideline: Do the work in a task

Event flags

32-bit per-task flags with ANY/ALL wait modes. Blocking / non-blocking / timeout waits. ISR-safe signaling with optional auto-clear for one-shot events.

Events
Width: 32-bit flags per task
Wait: ANY / ALL + timeout
ISR: Safe set/clear variants
Mode: Optional auto-clear
Goal: Low-latency coordination
Use case: ISR signals → task reacts

Message queues

Fixed-size bounded ring buffers. Lock-free fast paths for single producer/consumer. ISR-safe enqueue/dequeue variants for real-time pipelines.

Queues
Design: Fixed-size ring buffer
Fast-path: Lock-free SPSC
ISR: Safe variants
Use case: Control → audio task messages
Memory: Bounded, deterministic
Goal: Keep ISRs tiny

ISR interface

ISRs never block and don’t touch ready queues. Atomic flag-based communication keeps interrupt overhead minimal.

ISR
Rule: ISRs never block
Rule: ISRs don’t mutate ready queues
Mechanism: Atomic flag-based handoff
Goal: Ultra-low latency signaling
Benefit: Predictable interrupt timing
Practice: Do work in tasks, not ISRs

Architecture notes

Circular doubly-linked ready queues for O(1) enqueue/dequeue. Debugger-friendly inspection variables and built-in breakpoints for hard failures. The goal is a codebase you can reason about at 3am on a bench.